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PIC18F6585/8585/6680/8680
DS30491C-page 262
2004 Microchip Technology Inc.
FIGURE 20-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
20.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it to ‘0’. Since it is
also possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
Any read or write of CMCON will end the
mismatch condition.
b)
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
D
Q
EN
To RF1 or
RF2 pin
Bus
Data
Read CMCON
Set
MULTIPLEX
CMIF
bit
-
+
D
Q
EN
CL
Port pins
Read CMCON
RESET
From
other
Comparator
CxINV
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
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